Is Vivado 2026.1 still free?

Yes. AMD's Basic tier remains free with annual renewal, but it is feature-limited. From 2026.1, Vivado also requires a valid license file before it launches, even for Basic, configured through the Vivado License Manager or XILINXD_LICENSE_FILE.

Does System ILA work in the Vivado Basic tier?

No. System ILA is not available in Basic; it starts at the Core tier. Basic allows only a single instantiated ILA core with up to 5 probes, and excludes debug-insertion flows and IBERT.

Are encrypted bitstreams available in Vivado Basic?

No. Encrypted bitstream support starts at the Core tier. The RTL Encryptor Tool and Isolation Design Flow start at Pro and higher, so commercial designs with IP-protection needs should not assume Basic is enough.

Which Vivado tier do I need for Versal?

Versal designs require the Pro tier. Basic and Core do not cover Versal. RFSoC and Virtex UltraScale/UltraScale+ start at Core, while Alveo uses a dedicated Alveo tier.

What is the difference between Vivado Basic, Core, and Pro?

Basic is the free annual tier for small 7 Series and low-end UltraScale+ designs with limited debug and simulation. Core adds full debug, encrypted bitstreams, timing-closure reports, and incremental compile. Pro adds Versal and advanced implementation flows.

Vivado 2026.1 Licensing: What You Need to Know

AMD Vivado 2026.1 is not just a normal release with a pricing footnote. From 2026.1, Vivado moves to a tier-based licensing model: Basic, Core, and Pro as annual subscriptions, with Enterprise and Gold as perpetual options.^{[1], [2]}

The question is not "is Vivado still free?" AMD says Basic stays free with annual renewal.^[1] It is which parts of a real FPGA workflow are tier-gated. If you only synthesize a small 7 Series or Spartan UltraScale+ design, Basic may be enough. If you rely on System ILA, debug insertion, encrypted bitstreams, IBERT, DFX, timing-closure guidance, incremental compile, or larger devices, the answer changes quickly.

The Short Version

The most important small print:

Limited Basic debug

Small ILA use is possible, but System ILA and richer debug flows are tier-gated.

Limited XSIM in Basic

Basic includes limited XSIM simulation; full simulation starts at Core.

Core starts serious workflow comfort

Full debug, encrypted bitstreams, timing-closure reports, incremental compile, DFX, and broader devices.

Vivado 2026.1 licensing map showing Basic, Core, Pro, Enterprise and Gold tiers with practical workflow gates

There is also a new operational detail: from 2026.1, Vivado must find a valid license file before it launches, even for the free Basic tier; configure it through Vivado License Manager or XILINXD_LICENSE_FILE.^[3]

What Actually Changed

AMD's public licensing page describes five tiers:

Tier	Model	Practical reading
Basic	Free annual	Small 7 Series / low-end UltraScale+ builds; check debug, security, simulation, and flow limits.
Core	Paid annual	The practical minimum for many professional UltraScale+ workflows.
Pro	Paid annual	Needed when Versal and advanced flows enter the project.
Enterprise	Perpetual	Continuity path for teams that want ownership / version stability.
Gold	Perpetual + extended support	Long support window; the only tier that can disable Vivado's tool telemetry.

AMD says the new model starts with Vivado 2026.1, provides more price points, keeps IP licensing unchanged, keeps Vivado Lab Edition unchanged, and does not change the AMD University Program.^[1]

But "no change to IP licensing" is not the same as "every workflow remains available in Basic."

AMD also notes the 2026.1 tools collect usage telemetry; the option to disable it is limited to the Gold tier.^[1]

The Debug Trap: ILA Is Not System ILA

This is the first place I would check for a real project.

AMD's published licensing details say:

JTAG programming/communication is available in all tiers.
ILA is available in Basic by instantiation only — a single ILA core with up to 5 probes, each up to 1024 bits wide; designs needing more than 5 probes require Core or higher.
Debug insertion flows are not available in Basic.
System ILA is not available in Basic.
IBERT IP is not available in Basic.
System/processor debug remains available in all tiers.^[4]

If your design uses AXI-stream or AXI-mapped debug through System ILA, plan on Core or higher.

Regular ILA is more nuanced. A small hand-instantiated ILA for a few signals may be fine in Basic, but if your workflow is "add debug cores late, insert probes across a block design, or debug serial links with IBERT," Basic is the wrong assumption.

The Alternative: Open-Source Debug

If the Basic ILA is not enough, one good alternative is to move the debug strategy into your own RTL. fcapz is an open-source debug stack with an embedded logic analyzer, embedded I/O, JTAG-to-AXI, JTAG-to-UART, GUI/Web app tooling, and capture export to JSON, CSV, or VCD.^[6]

It will not replace IBERT or automatic debug insertion. But for waveform capture, scripted register access, or targeted internal visibility, it can remove the pressure to upgrade purely because Vivado Basic's built-in debug flow is constrained.

Simulation and Verification

Basic includes XSIM, but AMD lists it as limited simulation rather than full XSIM; full simulation starts at Core.^[4] AMD has not published an exact size limit, so treat Basic simulation as suitable for small RTL blocks, training designs, and quick sanity tests, not full SoC-style simulation, a large generated IP hierarchy, or a serious verification environment.

Timing Closure and Compile-Time Features

The Basic tier can feel fine early in a project and painful near timing closure.

In Basic:

Report QoR Assessment and Report QoR Suggestions are not available. These are Vivado reports that flag timing or congestion risks and suggest tool or constraint changes.
Intelligent Design Runs are not available.
Incremental compile for UltraScale / UltraScale+ is not available.
ECO flow remains available.^[4]

For a small design that closes comfortably, that may be acceptable. For a dense Spartan UltraScale+ design with tight timing and repeated implementation iterations, losing those timing-closure reports and incremental compile directly affects engineering time. If timing closure may be hard, price the license before you price the FPGA.

Security: Encrypted Bitstreams Are Not Basic

Security is another easy place to get surprised.

AMD lists encrypted bitstream support as not available in Basic but available in Core and above; the RTL Encryptor Tool and Isolation Design Flow start at Pro and higher.^[4]

For hobby, education, or lab-only designs this may not matter. For commercial embedded hardware or anything with IP-protection requirements, do not assume Basic is enough.

DFX, Tandem, and Advanced Flows

Basic also excludes several advanced implementation flows: DFX, Tandem Configuration for UltraScale / UltraScale+, and the advanced Versal configuration flows that start at Pro.^[4] Not a problem for a plain single-image build, but it matters if the architecture depends on partial reconfiguration, PCIe tandem startup, or modular implementation.

Device Support: Basic Is Broader Than "Tiny," But Not Universal

Basic supports more than many expect: all listed 7 Series families, Spartan UltraScale+, Artix UltraScale+, selected Zynq UltraScale+ MPSoCs, selected Kintex UltraScale / UltraScale+ devices, and Kria SOMs.^[5] But it does not cover everything: RFSoC and Virtex UltraScale / UltraScale+ start at Core, Versal starts at Pro, and Alveo uses a dedicated Alveo tier.^[5]

Renewals, Expiration, and CI

Basic is free, but it is still an annual license: AMD says subscriptions suspend active tool use until renewal if they expire.^[1]

For a solo developer that is mostly an admin task; for a team it is a CI risk. Decide where the license file lives, who owns renewal, whether XILINXD_LICENSE_FILE is set in automated builds, and whether an expired subscription could break an old maintenance branch. Development-kit vouchers also need tracking: AMD says kits still include a free one-year subscription, with the tier depending on the kit device, and a new subscription is required after that year.^[1]

Practical Checklist

A few practical checks can prevent surprises later:

Question	If yes, watch this
Do you need System ILA?	Basic is not enough; System ILA starts at Core.
Do you need regular ILA with many probes?	Basic limits ILA; consider Core or a scripted open-source debug core.
Do you need encrypted bitstreams?	Basic is not enough; plan Core or higher.
Do you need DFX or Tandem Configuration?	Basic is not enough; Versal advanced flows push toward Pro.
Do you need Versal?	Basic/Core are not enough; Versal starts at Pro.
Do you depend on fast iteration and timing-closure guidance?	Vivado timing-closure reports, Intelligent Design Runs, and UltraScale+ incremental compile are not Basic features.
Will the design be maintained for years?	Decide whether annual renewal or perpetual licensing fits the product lifecycle.

Think If You Need to Upgrade to 2026.1

Vivado Basic is not a toy tier. It covers real 7 Series, Spartan UltraScale+, Artix UltraScale+, and some Zynq UltraScale+ work. But a supported device does not mean every existing project should jump to 2026.1. If your current version is stable and you do not need new device support or tool fixes, staying on the known-good release can be the lower-risk decision; evaluate the tier model before upgrading, not after.

Upgrade deliberately when the benefits are clear:

you need new device support, such as Spartan UltraScale+ or newer Versal families
you need a 2026.1 tool fix, timing-closure improvement, or flow enhancement
your debug, security, simulation, and implementation flows fit the tier you plan to use, or you have an alternative such as fpgacapZero
your team and CI can manage annual licenses, and your maintenance plan accepts the new model

"The device is supported by Basic" is not the same as "the workflow is supported by Basic." The worst time to discover that System ILA, encrypted bitstreams, or incremental compile is tier-gated is after the board is routed and bring-up starts.

References

AMD Vivado Design Suite licensing options - public tier descriptions, pricing, subscription/perpetual models, FAQ, development-kit voucher notes, OS support table, and renewal notes.
AMD Vivado Design Suite overview - Vivado 2026.1 release overview and new tiered licensing model announcement.
UG973: Licensing - 2026.1 tier-based subscription licensing model and the requirement for a valid license file before Vivado launches.
AMD Adaptive SoC and FPGA Licensing FAQ - per-tier feature gating, including ILA probe limits, debug-insertion / System ILA / IBERT availability, simulation, timing-closure guidance tools, incremental compile, DFX, and security.
UG973: Release Notes, Installation, and Licensing - supported devices and tier-by-tier device-family availability for Basic, Core, Pro, Enterprise, and Gold.
fpgacapZero repository - open-source vendor-agnostic FPGA debug cores, including embedded logic analyzer, embedded I/O, JTAG-to-AXI, JTAG-to-UART, host tools, and supported FPGA-family wrappers.