New Vivado Licensing changes: What You Need to Know

AMD Vivado 2026.1 is not just a normal release with a pricing footnote. From 2026.1, Vivado moves to a tier-based licensing model: Basic, Core, and Pro as annual subscriptions, with Enterprise and Gold as perpetual options.^{[1], [2]}

The question is not "is Vivado still free?" AMD says Basic stays free with annual renewal.^[1] It is which parts of a real FPGA workflow are tier-gated. If you only synthesize a small 7 Series or Spartan UltraScale+ design, Basic may be enough. If you rely on System ILA, debug insertion, encrypted bitstreams, IBERT, DFX, timing-closure guidance, incremental compile, or larger devices, the answer changes quickly.

The Short Version

The most important small print:

There is also a new operational detail: from 2026.1, Vivado must find a valid license file before it launches, even for the free Basic tier; configure it through Vivado License Manager or global license variable.^[3]

What Actually Changed

AMD's public licensing page describes five tiers:

AMD says the new model starts with Vivado 2026.1, provides more price points, keeps IP licensing unchanged, keeps Vivado Lab Edition unchanged, and does not change the AMD University Program.^[1]

But "no change to IP licensing" is not the same as "every workflow remains available in Basic."

AMD also notes the 2026.1 tools collect usage telemetry; the option to disable it is limited to the Gold tier.^[1]

The Linux Flashpoint

One of the most controversial details was Linux availability in the free tier. Early coverage of the 2026.1 licensing model reported that Basic was shown as Windows-only, meaning Linux users would need Core or higher for current Vivado releases.^[7] After community backlash, AMD's current licensing table lists both Windows and Linux support across all tiers, including Basic.^[1]

The Debug Trap: ILA Is Not System ILA

AMD's published licensing details say:

• JTAG programming/communication is available in all tiers.
• ILA is available in Basic by instantiation only: a single ILA core with up to 5 probes, each up to 1024 bits wide; designs needing more than 5 probes require Core or higher.
• Debug insertion flows are not available in Basic.
• System ILA is not available in Basic.
• IBERT IP is not available in Basic.
• System/processor debug remains available in all tiers.^[4]

If your design uses AXI-stream or AXI-mapped debug through System ILA, plan on Core or higher.

Regular ILA is more nuanced. A small hand-instantiated ILA for a few signals may be fine in Basic, but if your workflow is "add debug cores late, insert probes across a block design, or debug serial links with IBERT," Basic may not fit that workflow.

The Alternative: Open-Source Debug

If Basic ILA does not cover your debug needs, one good alternative is to move the debug strategy into your own RTL. fcapz is an open-source and free debug stack with an embedded logic analyzer, embedded I/O, JTAG-to-AXI, JTAG-to-UART, GUI/Web app tooling, and capture export to JSON, CSV, or VCD.^[6]

With fcapz you can capture waveforms, poke AXI registers from scripts, or expose targeted internal state when you want visibility that is vendor-portable and controlled by your RTL.

Simulation and Verification

Basic includes XSIM, but AMD lists it as limited simulation rather than full XSIM; full simulation starts at Core.^[4] AMD has not published an exact size limit, so treat Basic simulation as suitable for small RTL blocks, training designs, and quick sanity tests, not full SoC-style simulation, a large generated IP hierarchy, or a serious verification environment.

Timing Closure and Compile-Time Features

The Basic tier can feel fine early in a project and painful near timing closure.

In Basic:

• Report QoR Assessment and Report QoR Suggestions are not available. These are Vivado reports that flag timing or congestion risks and suggest tool or constraint changes.
• Intelligent Design Runs are not available.
• Incremental compile for UltraScale / UltraScale+ is not available.
• ECO flow remains available.^[4]

For a small design that closes comfortably, that may be acceptable. For a dense Spartan UltraScale+ design with tight timing and repeated implementation iterations, losing those timing-closure reports and incremental compile directly affects engineering time. If timing closure may be hard, price the license before you price the FPGA.

Security: Encrypted Bitstreams Are Not Basic

Security is another easy place to get surprised.

AMD lists encrypted bitstream support as not available in Basic but available in Core and above; the RTL Encryptor Tool and Isolation Design Flow start at Pro and higher.^[4]

For hobby, education, or lab-only designs this may not matter. For commercial embedded hardware or anything with IP-protection requirements, do not assume Basic is enough.

DFX, Tandem, and Advanced Flows

Basic also excludes several advanced implementation flows: DFX, Tandem Configuration for UltraScale / UltraScale+, and the advanced Versal configuration flows that start at Pro.^[4] Not a problem for a plain single-image build, but it matters if the architecture depends on partial reconfiguration, PCIe tandem startup, or modular implementation.

Device Support: Basic Is Broader Than "Tiny," But Not Universal

Basic supports more than many expect: all listed 7 Series families, Spartan UltraScale+, Artix UltraScale+, selected Zynq UltraScale+ MPSoCs, selected Kintex UltraScale / UltraScale+ devices, and Kria SOMs. Device size still matters, and not every family is included: RFSoC and Virtex UltraScale / UltraScale+ start at Core, Versal starts at Pro, and Alveo uses a dedicated Alveo tier.^[5]

Renewals, Expiration, and CI

Basic is free, but it is still an annual license: AMD says subscriptions suspend active tool use until renewal if they expire.^[1]

For a solo developer that is mostly an admin task; for a team it is a CI risk. Decide where the license file lives, who owns renewal, whether XILINXD_LICENSE_FILE is set in automated builds, and whether an expired subscription could break an old maintenance branch. Development-kit vouchers also need tracking: AMD says kits still include a free one-year subscription, with the tier depending on the kit device, and a new subscription is required after that year.^[1]

Practical Checklist

A few practical checks can prevent surprises later:

Think If You Need to Upgrade to 2026.1

Vivado Basic is not a toy tier. It covers real 7 Series, Spartan UltraScale+, Artix UltraScale+, and some Zynq UltraScale+ work. But a supported device does not mean every existing project should jump to 2026.1. If your current version is stable and you do not need new device support or tool fixes, staying on the known-good release can be the lower-risk decision; evaluate the tier model before upgrading, not after.

Upgrade deliberately when the benefits are clear:

• you need new device support, such as Spartan UltraScale+ or newer Versal families
• you need a 2026.1 tool fix, timing-closure improvement, or flow enhancement
• your team and CI can manage annual licenses, and your maintenance plan accepts the new model

"The device is supported by Basic" is not the same as "the workflow is supported by Basic." The worst time to discover that System ILA, encrypted bitstreams, or incremental compile is tier-gated is after the board is routed and bring-up starts.

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