Production-grade FPGA IP cores and products, plus the open-source hardware we build and maintain — vision interfaces, space and networking links, video encoding, and debug tooling.
A high-performance MIPI CSI-2 aggregator core. Combine multiple camera sensor streams into a single unified data path with synchronized frame timing. Essential for multi-sensor fusion, surround-view systems, and advanced ADAS applications.
A hardware image signal processing pipeline: sensor corrections, debayer, white balance, and color correction at full sensor rate, behind any camera interface. For embedded vision systems that can’t depend on an SoC’s hardwired ISP.
A GigE Vision IP core optimized for robust, high-bandwidth video streaming over Ethernet. Designed for machine vision applications requiring reliable, uncompressed, low-latency image transfer.
A highly optimized, CoaXPress IP core for next-generation machine vision and industrial cameras. Engineered for low latency and deterministic high-throughput video transmission over coaxial cables.
The commercial tier of our MJPEG encoder: the same standards-compliant JPEG output scaled to 4Kp60 4:2:2, with closed-loop bitrate and frame-rate control in hardware, runtime configuration over AXI4-Lite, and an RTP/JPEG Ethernet streaming reference system. No external memory, latency of a few video lines.
An open-source SpaceWire link core in VHDL and Verilog with AXI4-Lite control and AXI4-Stream data, vendor-neutral clock-domain crossing, a dual-language cocotb regression, and an Arty A7 hardware example.
A suite of FPGA debug cores for real-time signal capture and analysis. Also features AXI4 and UART bridges to JTAG, flexible triggering mechanisms, and Python API.
An open-source Verilog Ethernet MAC with AXI4-Stream packet interfaces, AXI4-Lite control, MDIO management, MII/RGMII PHY support, jumbo frames, statistics, and checksum offload.
An open-source highly efficient synthesizable MJPEG encoder written in Verilog with AXI interfaces. Reaches 1080p30 performance even on low-end FPGAs with two selectable operating modes.
An agent skill that turns an HDL, RTL, or SoC architecture description into a clean SVG block diagram: clock-domain color coding, AXI-aware connections, CDC blocks, and geometry validation. Works with Claude Code and Codex.
A lightweight AXI4/AXI4-Lite interconnect generator. Describe your bus topology in YAML and automatically generate optimized Verilog RTL with mixed-protocol support.
A free, open-source Cyclic Redundancy Check (CRC) RTL generator. Optimized for high-throughput FPGA implementations, supporting custom polynomials and data widths.