Production-grade FPGA IP cores and products, plus the open-source hardware we build and maintain — vision interfaces, memory and networking, video encoding, and debug tooling.
A high-performance MIPI CSI-2 aggregator core. Combine multiple camera sensor streams into a single unified data path with synchronized frame timing. Essential for multi-sensor fusion, surround-view systems, and advanced ADAS applications.
A GigE Vision IP core optimized for robust, high-bandwidth video streaming over Ethernet. Designed for machine vision applications requiring reliable, uncompressed, low-latency image transfer.
A highly optimized, CoaXPress IP core for next-generation machine vision and industrial cameras. Engineered for low latency and deterministic high-throughput video transmission over coaxial cables.
A suite of FPGA debug cores for real-time signal capture and analysis. Also features AXI4 and UART bridges to JTAG, flexible triggering mechanisms, and Python API.
An open-source Verilog Ethernet MAC with AXI4-Stream packet interfaces, AXI4-Lite control, MDIO management, MII/RGMII PHY support, jumbo frames, statistics, and checksum offload.
An open-source highly efficient synthesizable MJPEG encoder written in Verilog with AXI interfaces. Reaches 1080p30 performance even on low-end FPGAs with two selectable operating modes.
A lightweight AXI4/AXI4-Lite interconnect generator. Describe your bus topology in YAML and automatically generate optimized Verilog RTL with mixed-protocol support.
A free, open-source Cyclic Redundancy Check (CRC) RTL generator. Optimized for high-throughput FPGA implementations, supporting custom polynomials and data widths.