What emacZero is
Most FPGA designs that need Ethernet reach either for a vendor MAC IP tied to one tool flow, or a hard MAC bound to specific silicon. emacZero is a third option: a self-contained Layer 2 MAC in portable Verilog 2001 that connects to your logic over standard AXI interfaces and to any external MII or RGMII PHY.
- AXI4-Stream TX/RX packet interfaces and an AXI4-Lite control/status register block for SoC integration.
- MII (10/100) and RGMII (10/100/1000) PHY interfaces, with the link speed selectable at runtime through a configuration register.
- MDIO master for PHY register access and link management.
- Framing done right: IEEE 802.3 FCS generation and checking, 64-byte minimum frame padding, and 12-byte inter-frame gap enforcement.
- Jumbo frames up to 9,018 bytes (parameterizable) and an IPv4/UDP TX checksum patcher so software does not have to compute checksums.
- Filtering and telemetry: optional multicast hash filtering, plus hardware counters for frames, bytes, CRC errors, frame sizes, broadcasts, and multicasts.
Integration paths
The RTL is written to drop into existing flows rather than assume one. The repository ships a minimal instantiation template for direct integration, a C99 bare-metal driver for the register interface, a LiteX module wrapper, and FuseSoC packaging. The DDR I/O primitives sit behind a vendor-agnostic wrapper layer with implementations for Xilinx and Intel devices, so the core itself stays portable.
Verification and measured results
The regression suite covers 35 test scenarios — CRC validation, FIFO behavior, loopback, and integration tests — run in CI with Icarus Verilog, plus Verilator lint. In hardware, the reference platform is a Digilent Arty A7-100T with a TI DP83848J MII PHY, sustaining ~95 Mbps of bidirectional UDP throughput at 100 Mbps full duplex with 1472-byte payloads — effectively line rate.
Resource cost on that Artix-7: the MAC core alone is about 1,858 LUTs and 1,801 flip-flops; the full reference demo, including the SoC around it, is about 9,959 LUTs, 19,254 flip-flops, and 4.5 block RAMs.
Frequently asked questions
What license does emacZero use?
Apache 2.0. Use the MAC, driver, and wrappers in commercial designs, modify them, and ship them without copyleft obligations.
Does it do gigabit?
The RGMII interface supports 10/100/1000 with runtime speed selection. Hardware validation to date has concentrated on the MII path at 100 Mbps on the Arty A7-100T; the RGMII path shares the same regression suite but has had less time on hardware, so qualify it on your own board like any other IP.
How do I talk to it from software?
Over the AXI4-Lite register block, using the included C99 bare-metal driver — or directly from fabric logic over AXI4-Stream if there is no CPU in the design. Statistics counters and the MDIO master are exposed through the same register interface.
Can bard0 help integrate it?
Yes. emacZero is maintained by bard0 design, and we help teams build networked FPGA systems around it — from camera-over-GigE pipelines with our MIPI CSI-2 Aggregator and FPGA ISP to debug instrumentation with fpgacapZero.
The RTL, driver, testbenches, and documentation are on GitHub. If you want help putting Ethernet into an FPGA design, get in touch.