Why SDI, and why on an FPGA?
SDI remains the backbone of professional video: uncompressed pictures with embedded audio, timecode, and metadata over a single 75 Ω coax run, with locked timing and no negotiation or compression stack in the path. Broadcast trucks, studios, live event production, medical imaging carts, and industrial inspection systems are built on it.
FPGAs are the natural home for SDI equipment. The serial rates map directly onto FPGA gigabit transceivers, the video arrives as a clean synchronous stream, and whatever sits between input and output runs at line rate with deterministic latency, whether that is conversion, processing, compression, or analysis.
What we deliver
SDI capture and generation, SD to 12G
Receive and transmit across the full SMPTE ladder: SD-SDI (ST 259), HD-SDI (ST 292), 3G-SDI (ST 424/425), 6G-SDI (ST 2081), and 12G-SDI (ST 2082), which carries up to 4Kp60 on a single link. Multi-link configurations are covered where the surrounding equipment requires them. We configure and bring up the FPGA transceivers, use vendor SMPTE SDI cores where they fit, and build custom framing where they don’t.
The whole signal path, not just the RTL
SDI is as much a board problem as a fabric problem. We design the path from the BNC in: adaptive cable equalizers, reclocking cable drivers, controlled-impedance routing guidance, and the reference clocking and genlock architecture the transmitter’s jitter budget depends on.
Processing between input and output
Once the stream is in the fabric as AXI4-Stream video, the pipeline is open: color-space and format conversion, up/down/cross conversion, frame synchronization, overlays and keying, plus correct handling of the ancillary data (SMPTE ST 291): embedded audio, timecode, and captions preserved, extracted, or inserted as the product requires.
Bridging SDI to everything else
Most projects connect SDI to another world: MIPI CSI-2 sensor front ends brought out over SDI, SDI capture into an edge AI inference pipeline, SDI-to-Ethernet streaming with compression like our mjpegZero encoder, or SDI-to-USB (UVC) capture. Same structure every time: SDI on one side, AXI4-Stream in the middle, the target interface on the other.
Verification & delivery
Delivery includes RTL verification, timing closure, board bring-up, and measurements on the target hardware, with documentation that lets your team own the design afterwards.
Why bard0
- Imaging and video is our core business. Our IP portfolio includes the FPGA ISP, the MIPI Aggregator, and the mjpegZero MJPEG encoder, so the pipeline around the SDI interface is designed by the same team.
- Multi-vendor experience. We work with AMD/Xilinx, Intel/Altera, and Microchip, and select the device against the target rates. 12G-SDI narrows the transceiver options, and we know where the lines are.
Frequently asked questions
What SDI rates can an FPGA handle?
The full SMPTE ladder: SD-SDI (ST 259), HD-SDI (ST 292), 3G-SDI (ST 424/425), 6G-SDI (ST 2081), and 12G-SDI (ST 2082), with up to 4Kp60 on a single coax link. The rate determines the transceiver and device family, so device selection is part of the work: not every FPGA reaches 12G rates, and we match the part to the target rates and the rest of the design.
Do you use vendor SDI IP or custom RTL?
Whichever fits the project. Vendor SMPTE SDI cores are a solid base on the devices they support; custom framing and processing logic makes sense where the vendor core doesn’t fit the device, the feature set, or the portability requirements. In both cases the transceiver configuration, clocking, and the pipeline around the core are engineered for the specific product.
Can you bridge SDI to MIPI, Ethernet, or USB?
Yes. Common shapes are SDI capture into a processing or AI pipeline, MIPI CSI-2 sensor front ends brought out over SDI, SDI-to-Ethernet streaming with compression, and SDI-to-USB capture devices. The FPGA gives all of these the same structure: SDI on one side, AXI4-Stream video in the middle, and the target interface on the other.
Do you handle embedded audio, timecode, and ancillary data?
Yes. SDI carries embedded audio, timecode, and other ancillary data (SMPTE ST 291) alongside the picture, and a correct design preserves, extracts, or inserts it as the product requires, not just the active video.
What about genlock and synchronization?
Broadcast chains expect equipment to lock to a house reference. We design the reference and clocking architecture together with the board-level equalizer and driver stages: genlock input, frame synchronization, and the jitter-sensitive clock path the SDI transmitter needs.
Tell us the rates and formats involved and what the system needs to do between the BNCs. We’ll assess device options, architecture, implementation effort, and cost.