fpgacapZero: Open-Source FPGA Debug Stack

What fcapz does

Vendor debug tools (ILA, SignalTap, Reveal, SmartDebug) are usually the fastest way to look inside a design on the bench, but they tie the debug method to one vendor's flow, license tier, and GUI — a poor fit for automation, remote bring-up, and multi-vendor projects.

fpgacapZero (fcapz) is an open-source debug stack compiled into the design itself: four cores driven over JTAG by a set of host tools, so the same captures used interactively on the bench can also run from scripts in CI or manufacturing tests. It uses the existing JTAG header — no extra board pins and no soft CPU required.

• ELA — embedded logic analyzer. Samples internal signals with flexible triggers (value match, edge/change detection) and pre/post-trigger capture, exporting to VCD, CSV, or JSON.
• EIO — embedded I/O. Reads fabric status signals and drives small debug controls at runtime, without dedicating board pins.
• JTAG-to-AXI4 master. Memory-mapped bus access for inspecting and poking registers while firmware is still unstable.
• JTAG-to-UART. Console-style communication with the design over the same cable.

Host tooling

Alongside the RTL, fcapz ships a Python API for automation, a CLI (fcapz) for quick captures, and a web frontend (fcapz-web) backed by a JSON-RPC server for interactive, remote, and shared bring-up. The JTAG transport is OpenOCD or Xilinx hw_server, depending on the board and flow.

The host tools are published on PyPI (Python 3.10+), so installation is one command:

pip install fpgacapzero

Captures export as VCD, CSV, or JSON, so the output goes into standard waveform viewers and diff tools, and scripted captures can be stored and compared across runs — the basis for using fcapz in CI regressions and manufacturing tests.

Where it fits

• Board bring-up. Confirm reset sequencing, clock-domain handshakes, sensor links, and host-interface state before software is ready.
• Driver and firmware work. Use JTAG-to-AXI to read and write the register map directly while the software stack is still moving.
• CI and regression captures. Scripted captures compared as JSON/CSV/VCD, kept with the test that produced them.
• Vendor-diverse designs. One debug pattern across Xilinx 7-series, UltraScale/UltraScale+, Lattice ECP5, Intel/Altera, Gowin, and Microchip PolarFire targets.
• Products that need service hooks. A small, controlled debug interface compiled into engineering or manufacturing builds — and removable from production bitstreams.

Resource cost: an 8-bit, 1024-sample ELA fits in roughly 600 LUTs plus half a BRAM. Wider probes and deeper capture memories scale the cost, mostly in BRAM.

Frequently asked questions

What license does fpgacapZero use?

Apache 2.0. Use it in commercial designs, modify it, and ship it in engineering or manufacturing builds without copyleft obligations.

Does it replace ILA or SignalTap?

No — it complements them. Vendor tools remain the shortest path for deep, device-specific bring-up. fcapz adds a second, scriptable visibility path that is part of the design source and independent of tool license tiers (relevant since the Vivado 2026.1 licensing changes, where designs with more than five ILA debug probes need a paid tier).

Which FPGAs does it support?

Wrappers ship for Xilinx 7-series, UltraScale/UltraScale+, Lattice ECP5, Intel/Altera, Gowin, and Microchip PolarFire. 7-series is validated in hardware on an Arty A7-100T; qualify the rest on your own board like any other IP block.

How do I install the host tools?

pip install fpgacapzero (Python 3.10+) installs the CLI, Python API, and web frontend from PyPI. The RTL cores come from the GitHub repository and are instantiated in your design like any other IP.

Can bard0 help integrate it?

Yes. fpgacapZero is maintained by bard0 design, and we help teams plan debug instrumentation into a design — including alongside our IP cores like the MIPI CSI-2 Aggregator and FPGA ISP.