A running list of things that make an agentic loop useful on FPGA work: skills that teach an agent a specific job, tools it can drive from a command line, and the standards underneath. It is a companion to Agentic AI for FPGA Design: How the Loop Works, and it grows as we find or build something worth listing. Nothing here is sponsored, and we use what we list.
Skills
A skill is a folder with a SKILL.md file in it: a name, a description, and instructions for one job, optionally with scripts and reference files alongside. The agent loads only the name and description at startup and reads the full instructions when a task matches, so a set of skills costs almost nothing until one is needed.[1] The format started at Anthropic, is published as an open standard, and is now read by a long list of agents rather than one.[2]
For FPGA work this matters because the useful knowledge is procedural. Which report to open after synthesis, what a warning actually means, how your project names its files: that is exactly what a skill holds, and exactly what you would otherwise retype into a prompt every session.
hdldiagZero bard0 design
Turns an HDL, RTL or SoC architecture description into a clean SVG block diagram. It walks the hierarchy from the top module, classifies the interfaces it finds, colours blocks by clock domain, marks clock domain crossings, and leaves out the clock, reset, JTAG and debug signals that make a diagram unreadable. The geometry is validated, so lines do not run through blocks.
The diagram nobody drew, or the one that stopped matching the code three revisions ago. Ask the agent to draw the top level and you get an SVG you can put in a review, a specification or a handover.
Install it in Claude Code as a plugin, or run python install.py from the repository for other runtimes. Python 3.10 or newer, standard library only, MIT licensed.
Tools the loop drives
The loop needs tools that run from a command line and report in text. These are the open-source ones the companion repository uses or builds on.
Icarus Verilog
Verilog and SystemVerilog simulator. Compiles and runs a testbench from two commands and writes whatever the testbench prints to standard output.
GHDL
VHDL simulator, and a synthesis front end that can hand a design to Yosys. The VHDL half of the companion repository runs on it.
Yosys
Open-source synthesis. Gives the agent a vendor-independent check that a design elaborates, infers no latches, and costs roughly what you expected in cells and flops, without waiting for a vendor flow.
OSS CAD Suite
A single binary bundle of the open-source flow: Yosys, GHDL, Icarus Verilog, nextpnr, the formal tools and the programmers, for Linux, macOS and Windows. The fastest way to get an agent a working toolchain on a fresh machine.
cocotb
Testbenches written in Python, driving VHDL or SystemVerilog through the simulator you already use. Worth knowing about because agents write Python more reliably than they write SystemVerilog testbenches.
Standards worth knowing
Agent Skills
The open format behind the skills above: a folder, a SKILL.md, optional scripts and references. Write a skill once and it is read by any agent that supports the standard.
Model Context Protocol
The open standard for connecting an agent to an external system, so a tool or a data source can be exposed once and used by any client that speaks it. Relevant when the thing you want the agent to reach is a server or a database rather than a command.
The agents themselves
Installing and signing in to Claude Code, OpenAI's Codex CLI or Cursor is covered separately, in Setting Up Claude Code and Codex CLI for the FPGA Loop, along with the vendors' own guides and videos.
References
2 sources
- Anthropic, "Agent Skills" in the Claude Code documentation: skill structure, where skills are installed, and how they load.
- "Agent Skills": the open standard, its specification, and the clients that support it.
Our FPGA and AI training sets this loop up on your own tools and designs, with the checks and limits in place.
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