What the aggregator does
Most SoCs and FPGAs have a limited number of MIPI CSI-2 receiver ports — often fewer than the number of cameras a modern vision system needs. The MIPI Aggregator solves that mismatch: it receives several independent CSI-2 camera streams and combines them into one outgoing CSI-2 link, using virtual channels to keep every stream separately identifiable downstream.
- Multiple sensors in, one link out. Independent CSI-2 inputs are arbitrated and interleaved into a single unified data path with synchronized frame timing.
- Standards-faithful packet handling. Data types, virtual channels, line and frame boundaries, and error-check fields are preserved, so the receiving SoC sees clean, compliant CSI-2 — not a proprietary stream format.
- Virtual channel remapping. Each input is assigned its own virtual channel on the output link, so downstream software can split the streams back out per camera.
- Debug visibility from day one. Packet, frame, and error counters per input, so bring-up problems are diagnosed with data instead of guesswork.
Designed for GMSL2 and FPD-Link camera systems
In automotive and industrial systems, cameras rarely sit next to the processor — they are meters away, connected over coax or shielded twisted pair through GMSL2 (Analog Devices / Maxim) or FPD-Link (TI) SerDes links. On the receiving end, a deserializer converts each link back into standard MIPI CSI-2.
That is exactly where the aggregator fits: placed behind a quad GMSL2 or FPD-Link deserializer, it merges the recovered CSI-2 streams — four surround-view cameras, a driver-monitoring camera plus external views, or a heterogeneous mix of resolutions — into one CSI-2 link into the SoC or the FPGA processing pipeline. The result: remote multi-camera capture without burning a CSI-2 receiver port per camera.
Applications
- Surround-view and ADAS. Multiple vehicle cameras fused into one synchronized stream for perception and viewing systems.
- Robotics and drones. Multi-camera rigs for navigation, obstacle detection, and mapping on platforms where every CSI-2 port and every watt counts.
- Machine vision and inspection. Multi-angle capture into a single processing pipeline with deterministic frame alignment.
- Stereo and depth systems. Paired sensors delivered with synchronized frame timing for downstream disparity processing.
Integration and delivery
- Standard AXI interfaces. Video moves over AXI4-Stream, and configuration and status are exposed through an AXI4-Lite register interface — so the core drops into existing Vivado/Platform Designer block designs and is controlled from software like any other memory-mapped peripheral.
- Vendor-portable RTL. Targeted at AMD/Xilinx devices and portable to Intel/Altera, Lattice, Microchip, and Efinix families, with the D-PHY front end adapted to the target device.
- Configurable to your sensor lineup. Input count, data types, and output link configuration are sized against your cameras' resolution, bit depth, and frame rate during evaluation.
- Delivered as a working system. RTL, verification environment, integration documentation, and engineering support — including help with the sensor and deserializer bring-up around the core. Our image and video pipeline services cover the rest of the chain, from ISP steps to edge AI inference on the aggregated streams.
Frequently asked questions
Does the MIPI Aggregator work with GMSL2 or FPD-Link cameras?
Yes. GMSL2 and FPD-Link deserializers output standard MIPI CSI-2, which is exactly what the aggregator consumes. A typical arrangement places the aggregator behind a quad deserializer so four remote coax or STP cameras merge into a single CSI-2 link into the SoC or FPGA processing pipeline.
How many cameras can be aggregated into one CSI-2 link?
The core is configurable. CSI-2 virtual channels allow many streams to share one link, and the practical limit is set by the aggregate bandwidth of the output link versus the resolution, bit depth, and frame rate of the input cameras. We size the configuration against your sensor lineup during evaluation.
Which FPGAs does the MIPI Aggregator support?
The core is vendor-portable RTL. It has been targeted at AMD/Xilinx devices and can be ported to Intel/Altera, Lattice, Microchip, and Efinix families; the D-PHY front end is adapted to the target device’s transceiver or I/O capabilities.
How is the core delivered and licensed?
The core is delivered as RTL with a verification environment, integration documentation, and engineering support. Licensing terms depend on the project — request the product brief for details and current deliverables.
Building a multi-camera system? Tell us your sensor lineup, SerDes setup, and target device — we’ll come back with the product brief and a concrete assessment of fit.